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Innovation Japan 2019 (August 29-30, 2019)


Innovation Japan 2019
Surface of the substrate is　etched by making use of graphene catalyst

August 29-30, Innovation Japan 2019 were held in Tokyo Big Sight. New topics of manufacturing process in this exhibition are picked up.


Picture 1. Relationship of sort of graphene and etching depth


Figure 1. Fabrication sample of etching method using graphene
Oosaka University introduced a unique manufacturing process using graphene, which is a new and old Nano size material. In this process, first of all, a graphene sheet is put on the substrate, such as silicon wafer, and then, the substrate is directly wet etched by water series etchant. In this time, area with graphene only is etched selectively because of graphene catalyst function, on the other hand, area without graphene is not etched.

Of course, it's possible to pattern graphene film by use of photolithography methods using graphene dispersion liquid for fine patterning. After patterning, graphene film is removed finally. Compared to the dry etching method, process damage can be greatly reduced, on the other hand, compared to the conventional wet etching method, anisotropic aspect and etching depth are higher, as a result, it's easy to form pattern with high aspect ratio.

And also, as picture 1, it's possible to control etching depth by kind of graphene sheet, such as, hyd-rGO, GO, and amm-rGO. By the way, etching rate is very low, same as a few dozen nm/h at the present moment.

Support carrier mobility and driving stability of oxide-TFT by homo stacking structure


Figure 2. Structure and cross-sectional SEM image of 2-layer oxide-TFT
Aikawa research laboratory of Kogakuin University appealed an original oxide-TFT. As figure 2, in this device, active layer is composed of 2 layers, such as low doping ISO (In-Si-O) and high doping ISO. In general, it's difficult to support carrier mobility and driving stability in oxide-TFTs. By contrast, this new structure, this trade-off relationship could be resolved by homo stacking semiconductor layer.

Its carrier mobility is high same as 17.4 cm2/Vs, which is higher that of the conventional IZGO-TFT. Furthermore, driving stability is superior, such as ΔVon＝0.2V, and also, ON/OFF current ratio is 107 and over. Of course, ISO films can be deposited at low temperature (RT - 250℃) by the conventional sputtering methods, and patterned by the conventional photo-etching method, too.

μLEDs are integrated by direct etching of the substrate

The research group (Prof.Honda, et.al.) of Kogakuin University reported integration technology of μLED, which is a next generation direct imaging display.


Picture 2. Integration of μLED by Micro-cup array
In this technology, array pattern of pixel and electrode is formed in advance by directly deep etching treatment of the substrate, for example, silicon wafer. The next, μLED chips are mounted on completed ditch by manual or mechanical work (pick & place). As a result, crosstalk can be minimized, and also, light extraction efficiency can be increased, too.

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