The 79th JSAP Autumn Meeting, 2018
Control technologies of Vth in oxide-TFT and organic-TFT were cranked-up

September 18 - 21, The 79th JSAP Autumn Meeting, 2018 was held in Nagoya International Congress Center. Topics of OLED, oxide-TFT, organic-TFT, and CNT-TFT are closed up based on the proceeding.

EIL and ETL of inverted OLED are optimized

First, as regards OLED, Shinshu University reported that electron injection layer (EIL) and electron transporting layer (ETL) of inverted OLED were optimized.

In this experiment, firstly, the glass substrate with ITO electrode was treated by O2 plasma process. The next, ammonium hydroxide liquid of ZnO was spin-coated, and then, the substrate was annealed at 300 ℃. Subsequently, polyethylenimine (PEI) was dip-coated, and then, annealed at 120 ℃. As a result, Nano size EIL, composed of ZnO/PEI double layers was formed. The next, ETL material and F8 were deposited. And then, Cs2CO3 was doped into ETL/EIL at 1 mol% or 5 mol% of doping density as a n type dopant. Subsequently, TFB was coated on PDMS stamp, and then, it was transferred to F8 film by the transfer process. Finally, MoO3 film and Ag film were deposited as a hole transporting layer and anode by the vacuum evaporation method.

Figure 1 shows J-V-L curves of pilot-produced device. Operating voltage of this device was decreased same as 1.2 V by doping of Cs2CO3. And also, maximum external efficiency of device without Cs2CO3 was mere 1.0 %, on the other hand, those of device with Cs2CO3 (doping ratio：1 mol% and 5 mol%) were 1.7 % and 2.5 % respectively. This is reason why efficiency is increased by acceleration of electron injection due to improvement of electron transporting characteristic and increase of band bending in boundary of EIL and F8.

Vth of oxide-TFT is controlled by UV annealing

As concerns oxide-TFT, the research group of Hitachi and Hitachi Metals reported annealing effect against ZTO-TFT.

Fig.3 Id-Vg characteristics of TFT2)

Fig.2 Schematic cross-section of TFT2)

In this experiment, as figure 2, the conventional back channel structure in a-Si TFT field was adopted as TFT structure. Channel length and width were 10 μm and 100 μm respectively. Channel layers (ZTO series oxide/IZO) and Mo source/drain electrodes were deposited at room temperature by the DC magnetron sputtering method. And also, test device was annealed by conventional annealing process (300 ℃, atmosphere) and UV annealing process (200 ℃, 40 mW/cm²).

Figure 3 shows Id-Vg characteristics of TFTs. Vth of treated device by the atmosphere annealing was -13.5 V, on the other hand, that of treated device by UV annealing was -3.5 V. And also, in UV annealed device, high carrier mobility was obtained same as 29.5 cm²/V･s. In short, it's possible to not only lower process temperature, but also, to increase carrier mobility and to control Vth, too.

ΔVth of organic-TFT is suppressed by use of hydrophobic gate dielectric

About organic-TFT, the research group of University of Tokyo and National Institute of Advanced Industrial Science and Technology (AIST）announced characteristics of all solution process device with hydrophobic gate dielectric.

Fig.4 (a)(b) Bias stress effects on transfer characteristics (Vd=−40 V) with two different gate dielectric. Gate dielectric layer is (a) Cytop and (b) SiO2, respectively. (c)ΔVth of TFT with different gate dielectric3)

In this time, first of all, a hydrophobic perfluoro polymer (Cytop) film was spin-coated as a gate dielectric. The next, Ag source/drain electrodes were printed by the SuPR-NaP method, which was possible to print speedy and easily. And then, a semiconductive polymer (PDVT-10) was deposited as a semiconductor layer by the push-coating method. As a result, a bottom-gate bottom-contact TFT was formed.

Figure 4 shows bias stress effects on transfer characteristics (Vd=−40 V) in N2 environment. As figure 4-(a), drain current of device with Cytop gate dielectric was decreased by mere 3 % and under. In short, bias stress stability was sufficient. On the other hand, as figure 4-(b), drain current of the reference device with SiOx gate dielectric and evaporated Au S/D electrodes was greatly decreased by 60 % and over due to occurrence of vth shift. Figure 4-(c) shows ΔVth of TFT with different gate dielectric. Vth shift of device with Cytop gate dielectric was greatly suppressed.

Strain in channel region of CNT-TFT is locally suppressed for wearable device

As concerns CNT-TFT, Nagoya University reported a CNT-TFT with stretchable characteristic for various wearable device.

Fig.6 ON and OFF currents as a function of externally applied tensile strain4)

Fig.5 Measured strain induced at channel region as a function of externally applied tensile strain4)

Pilot-produced device is composed of PDMS film substrate, CNT channel layer, CNT transparent electrodes, and Al2O3 gate insulator. A polymer with relatively high Young's modulus was coated in channel region, due to local control of strain.

The device was turned at gate voltage = 5 V. Carrier mobility and ON/OFF current ratio were 7.2 cm²/V･s and 10⁵ respectively. Figure 5 shows measured strain induced at channel region as a function of externally applied tensile strain. Strain at channel region was suppressed by 14 % of that of externally applied strain. Figure 6 shows ON and OFF currents as a function of externally applied tensile strain. If the device was stretched by 35 %, drain current was not changed. It suggested that local control of strain was effective.


Reference
1)Taguchi, et.al.：Effects of Multi-layered Nano-hybrid Electron Buffer Layers for Improving the Blue Light Propaties of Inverted Polymer Light Emitting Diodes , The 79th JSAP Autumn Meeting, 2018, 11-238 (2018.9)
2)Moritsuka, et.al.：Evaluation of the high mobility Oxide TFTs by low temperature anneal, The 79th JSAP Autumn Meeting, 2018, 16-068 (2018.9)
3)Kitahara, et.al.：Stable Operation of Solution-Processed Organic Thin-Film Transistors Based on Ultrahydrophobic Carrier Transport Interface, The 79th JSAP Autumn Meeting, 2018, 11-215 (2018.9)
4)Nishio, et.al.：Low-voltage operable, stretchable carbon nanotube thin-film transistors with local strain control layer, The 79th JSAP Autumn Meeting, 2018, 15-160 (2018.9)